Course Content
The design of a digital integrated circuit encompasses the need for multiple front-end and back-end models for standard-cells, I/O cells and memory IPs. This course will cover the development of standard cell libraries including the functional, timing and physical models required for the RTL-to-GDS design flow. Students will be able to design a standard cell library and perform cell characterization for sequential and combination blocks through assignments, exposing them to the front-end flow. Concepts on synthesis, floorplanning, placement, routing and verification will be covered. The designed standard cell library will be used in an open-source RTL-to-GDS design flow to design a custom design IP by the students thereby providing exposure to the physical back-end flow. Physical verification concepts like LVS, DRC and antenna checks will also be covered.
Text / References
- 1 1- Digital Integrated Circuits - a design perspective, Rabaey, Chandrakasan, Nikolic, Pearson, Second Edition, 2016, Pearson India Education Services Private Limited. 2- CMOS VLSI Design - A circuits and systems perspective, Neil Weste, David Harris, Ayan Banerjee, Pearson, Third Edition, 2011.